Generally, successive approximation register (SAR) analog to digital converters (ADC) can generate a digital code representing the magnitude of an input voltage (VIN). SAR ADCs can operate in two phases, namely a sampling phase and a bit trial phase. During the sampling phase, the input voltage can be acquired. During the bit trial phase, the input voltage can be compared against test voltages to determine whether the input voltage is greater than or less than the respective test voltages. SAR ADCs can operate bit by bit, comparing the input voltage initially to an analog voltage value corresponding to the most significant bit (MSB), deciding upon the value of the MSB and thereafter comparing the input voltage to an analog voltage value representing a combination of the selected MSB and a candidate value for the next lower bit position. The bit trial process operates incrementally across all bit positions from the MSB to the least significant bit (LSB) position until a complete digital code is generated that corresponds to the input voltage.